The present disclosure relates generally to field effect transistors. More particularly, the present disclosure relates to scaling of field effect transistors.
Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. As channel lengths are reduced, drive currents increase, which is beneficial for circuit performance. However, leakage currents increase as well. Transistor leakage currents are traditionally controlled by introducing controlled amounts of impurities (dopants) into the channel region of the device, and by tailoring the source/drain lateral and vertical doping distributions. Although these approaches are effective in shoring up the potential barrier internal to the metal oxide semiconductor (MOS) transistor and therefore reducing the leakage current, they can also contribute to degraded drive current and increased parasitic capacitance. Given traditional MOS transistor design and architecture, there are only limited solutions to the trade-off between drive current, leakage current, parasitic capacitance and resistance, and manufacturing complexity/cost.